{"id":15096,"date":"2021-06-01T15:48:18","date_gmt":"2021-06-01T13:48:18","guid":{"rendered":"https:\/\/www.codemotion.com\/magazine\/?p=15096"},"modified":"2022-01-05T20:02:44","modified_gmt":"2022-01-05T19:02:44","slug":"embedded-processing-in-programmable-logic","status":"publish","type":"post","link":"https:\/\/www.codemotion.com\/magazine\/ai-ml\/machine-learning\/embedded-processing-in-programmable-logic\/","title":{"rendered":"Embedded Processing in Programmable Logic"},"content":{"rendered":"\n<p>In the <a href=\"https:\/\/www.codemotion.com\/magazine\/dev-hub\/machine-learning-dev\/fpga-programable-logic-benefits\/\" class=\"ek-link\">first article<\/a> in this series co-produced with <a href=\"https:\/\/eu.mouser.com\/\" target=\"_blank\" rel=\"noreferrer noopener\" class=\"ek-link\">Mouser Electronics<\/a>, we explored the range of FPGA devices produced by Xilinx and discussed the benefits of adopting such a system for developers, engineers, and end-users alike. Now, let\u2019s dig a little deeper and discover what makes an FPGA tick.<\/p>\n\n\n\n<p>The <strong>programmable logic<\/strong> found in FPGAs is an excellent solution for implementing parallel processing structures. Although Programmable Logic (PL) is ideal for dealing with issues such as finite impulse response filters, image processing pipelines, and motor control algorithms, sometimes serial processing is necessary.<\/p>\n\n\n\n<p>Situations in which this is the case include implementing communication protocols, graphical user interfaces or control, configuration, and status reporting of IP blocks. Serial processing is also essential if we want to work with advanced open-source frameworks and languages such as TensorFlow, OpenCV and Python.&nbsp;<\/p>\n\n\n\n<p>Aided by programmable logic, there are several options open to us if we want to implement embedded processors with programmable logic devices. Taking a broad view, we can define these in two discrete groups:<\/p>\n\n\n\n<ul class=\"is-style-default wp-block-list\"><li><strong>Heterogeneous System-on-Chip<\/strong>: Combining programmable logic with a processing system, the processing solution of these heterogeneous system-on-chip solutions is tough on the device\u2019s silicon. This solution consequently offers outstanding performance but only limited configuration flexibility because of the processing solution.&nbsp;<\/li><\/ul>\n\n\n\n<ul class=\"is-style-default wp-block-list\"><li><strong>Soft-Core Embedded Processors<\/strong>: Programmable logic resources such as flip flops (FF), look-up tables and BRAMs (Block RAM) are used to implement soft-core processors. Consequently, the processors offer more configuration possibilities, but their performance is often negatively impacted.&nbsp;<\/li><\/ul>\n\n\n\n<p>As we will discover, both solutions &#8211; heterogeneous SoC and soft-core embedded &#8211; offer a variety of use cases across several exciting applications. <\/p>\n\n\n\n<p>Additionally, it is possible to implement additional soft-core processors in the programmable logic of heterogeneous SoCs.\u00a0 This is not unusual and can be used to create a big.LITTLE system that enables time for essential tasks to be off-loaded.\u00a0<\/p>\n\n\n\t\t\t\t<div class=\"wp-block-uagb-table-of-contents uagb-toc__align-left uagb-toc__columns-1  uagb-block-1f8887e6      \"\n\t\t\t\t\tdata-scroll= \"1\"\n\t\t\t\t\tdata-offset= \"30\"\n\t\t\t\t\tstyle=\"\"\n\t\t\t\t>\n\t\t\t\t<div class=\"uagb-toc__wrap\">\n\t\t\t\t\t\t<div class=\"uagb-toc__title\">\n\t\t\t\t\t\t\tTable Of Contents\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<div class=\"uagb-toc__list-wrap \">\n\t\t\t\t\t\t<ol class=\"uagb-toc__list\"><li class=\"uagb-toc__list\"><a href=\"#embedded-processors-in-xilinx\" class=\"uagb-toc-link__trigger\">Embedded Processors in Xilinx<\/a><li class=\"uagb-toc__list\"><a href=\"#soft-core-processors-spoilt-for-choice\" class=\"uagb-toc-link__trigger\">Soft-Core Processors &#8211; spoilt for choice!<\/a><li class=\"uagb-toc__list\"><a href=\"#the-biglittle-approach\" class=\"uagb-toc-link__trigger\">The big.LITTLE Approach<\/a><li class=\"uagb-toc__list\"><a href=\"#software-development\" class=\"uagb-toc-link__trigger\">Software Development\u00a0<\/a><li class=\"uagb-toc__list\"><a href=\"#conclusion\" class=\"uagb-toc-link__trigger\">Conclusion\u00a0<\/a><\/ol>\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\n\n\n<h2 class=\"wp-block-heading\" id=\"h-embedded-processors-in-xilinx\"><strong>Embedded Processors in Xilinx<\/strong><\/h2>\n\n\n\n<p>The <strong>Zynq-7000 SoC<\/strong> and <strong>Zynq MPSoC<\/strong> product families in the <strong>Xilinx <\/strong>range both offer embedded processors. Devices from these lines offer genuinely heterogeneous processing systems on the same silicon. In architectural terms, the processor system initially boots in the manner of a traditional processor before subsequently configuring the <a href=\"https:\/\/www.codemotion.com\/magazine\/dev-hub\/machine-learning-dev\/where-to-use-programmable-logic\/\" target=\"_blank\" rel=\"noopener\">programmable logic.&nbsp;<\/a><\/p>\n\n\n\n<p>First introduced in the Zynq-7000 SoC, Xilinx\u2019s product combines programmable logic with dual or single-core 32-bit Arm Cortex-A9 processors.&nbsp;<\/p>\n\n\n\n<p>Unsurprisingly, the processing system also provides peripherals that can be used for both volatile and non-volatile memory, as well as a number of interfaces such as Ethernet, UART and CAN.&nbsp;&nbsp;<\/p>\n\n\n\n<p>The Cortex-A9 cores also include a floating-point unit and a NEON engine (or &#8220;MPE&#8221; Media Processing Engine) in order to support high-performance applications. Large data sets can be processed in parallel, thanks to the NEON engine, using a single instruction against multiple data (SIMD). <\/p>\n\n\n\n<p>Image and audio processing benefit from this in particular, as do similar applications in which data sets need to be processed using simple instructions (e.g. multiply and add) repetitively, with little control code. In such applications, performance can be noticeably improved by leveraging the SIMD unit.<\/p>\n\n\n\n<p><strong>Advanced eXtensible Interfaces<\/strong> (AXI) are used to effect data transfer between the processing system and the programmable logic. This allows either the processor system or the programmable logic to initiate the transaction. Data can thus be easily transferred to and from the processor system\u2019s DDR memory.&nbsp;<\/p>\n\n\n\n<p>Because it combines the processing system and programmable logic in this way, the Zynq-7000 series is an exceptional choice for applications such as image processing, robotics, and augmented reality that require both serial and parallel processing.&nbsp;<\/p>\n\n\n\n<p>Both sides of this pairing can be adapted to improve connectivity and make use of the support offered to a broad range of frameworks and applications. Central elements or algorithms can be accelerated using programmable logic, while the processing system benefits from Embedded Linux solutions.&nbsp;&nbsp;<\/p>\n\n\n\n<p>Combining PS (processing system) and PL provides for a more responsive and deterministic solution. The table that follows provides a simple illustration based on implementing AES encryption.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td>Operating System<\/td><td>Processor System Clocks<\/td><td>PS Clocks with Programmable Logic<\/td><td>Reduction in Processing Time<\/td><\/tr><tr><td>Baremetal<\/td><td>28574<\/td><td>7104<\/td><td>75%<\/td><\/tr><tr><td>FreeRTOS<\/td><td>28368<\/td><td>7104<\/td><td>75%<\/td><\/tr><tr><td>Linux<\/td><td>36662<\/td><td>15644<\/td><td>54.8%<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>Processing capabilities underwent a major increase as the Zynq-7000 SoC evolved to become the next-generation Zynq MPSoC, and the latest logic fabric was added. Heterogeneous processors were included for the first time, giving developers the opportunity to deal with multiple challenges within the same device.&nbsp;<\/p>\n\n\n\n<p>The Zynq MPSoC processing system incorporates:&nbsp;<\/p>\n\n\n\n<ul class=\"is-style-default wp-block-list\"><li>Application Processing Unit \u2013 quad or dual 64-bit Arm Cortex-A53 processors<\/li><li>Real Time Processing Unit \u2013 dual lockstep 32-bit Arm Cortex-R5 processors<\/li><li>Platform Management Unit \u2013 Triple Modular Redundant 32-bit MicroBlaze processor, implemented in silicon<\/li><li>Graphics Processor Unit \u2013 Arm Mali-400 MP GPU&nbsp;<\/li><\/ul>\n\n\n\n<p>The <strong>MPSoC <\/strong>processing system includes four processing groups available to the developer for programming but also offers a configuration security processor that allows engineers to implement safety and security processing and security event responses.&nbsp;<\/p>\n\n\n\n<p>Having such a broad array of processing solutions allows for single-chip solutions to be created for many applications. In the automotive field, for example, complex algorithms and user interfaces can be implemented using the APU and GPU while real-time control and vehicle control interfacing can utilise the RPU, designed and certified for ISO26262 or IEC6508 applications.&nbsp;<\/p>\n\n\n\n<p><strong>AXI <\/strong>interfaces are also used to enable communication between the PS and PL, although this time they replace 32-bit interfaces. 128-bit interfaces increase the throughput between PS and PL to a significant degree.<\/p>\n\n\n\n<p>High-performance vision-based machine learning applications, such as those often used in automotive or other edge-based solutions can be implemented as a result of this high bandwidth capability. The Zynq-7000 SoC and Zynq MPSoC class of devices consequently offer the highest performance processor systems around.&nbsp;<\/p>\n\n\n\n<p>To see this at work, consider the image processing application example at Figure 1.&nbsp; Image data is transferred between the processor system and the programmable logic to implement the desired algorithm.<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/lh4.googleusercontent.com\/PdZ5bjdyN-7THpYEP5-w0hkELVd-p0jUPIt-0ptr0jiCFPY3gH6ZPQafVjqfOuu9b9uq0yJESUAi_4g434p3GxlBWmIr0PoyYOjUr7Z8UxWh_zAAOJUnwvG-Ke6y9RL-O6JtmvE\" alt=\"Diagram: Zynq MPSoC Processing System Interfacing with PL Image Processing Chain.\"\/><figcaption>Zynq MPSoC Processing System Interfacing with PL Image Processing Chain.<\/figcaption><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-soft-core-processors-spoilt-for-choice\"><strong>Soft-Core Processors &#8211; spoilt for choice!<\/strong><\/h2>\n\n\n\n<p>An unlimited choice exists in the Xilinx ecosystem for <strong>soft-core processors<\/strong>. The FF, LUTs (Local User Terminal), and RAMs of Xilinx FPGAs can be used to implement any processor described in RTL.&nbsp;<\/p>\n\n\n\n<p>The most popular choices include:<\/p>\n\n\n\n<ul class=\"is-style-default wp-block-list\"><li><strong>MicroBlaze<\/strong> \u2013 a 32-bit processor, a range of configurations from the controller to full MMU (Memory Management Unit) support capable of running embedded Linux are possible;<\/li><li>Arm Cortex-M1 \u2013 with a small logic footprint and great code density, courtesy of the Thumb Instruction set, this is a 32-bit FPGA implementation of the popular Cortex-M0;<\/li><li>Arm Cortex-M3 \u2013 another 32-bit implementation, this time of the Cortex-M3 processors. Full support of MMU and OS are on offer alongside good code density derived from Thumb\/Thumb2 instruction set support. A popular choice for Internet of Things applications.<\/li><li>RISC-V \u2013 open-source, 32\/64\/128-bit instruction set. RISC-V compliant implementations are available from a number of IP vendors for use in Xilinx FPGAs. Highly customizable,&nbsp; like MicroBlaze, RISC-V can also run embedded operating systems including Linux.&nbsp;<\/li><\/ul>\n\n\n\n<p>Although a soft-core processor inevitably provides less performance than a hard silicon instantiation, the greater configuration possibilities and adaptability of the soft-core option means that a much more highly customized solution can be implemented. <\/p>\n\n\n\n<p>A soft-core processor can also be portable, covering the needs of several devices or even vendors (depending upon the precise selection of processor).<\/p>\n\n\n\n<p>As with hard silicon processors, AXI is often the interface of choice to connect peripherals to soft-core equipment. In this context, \u201cperipherals\u201d includes DDR memory interfaces, UARTs, and popular processor interfaces such as I2C and SPI. Figure 2 provides an illustration: a MicroBlaze processor configures and controls a high-speed image processing pipeline.&nbsp;<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/lh5.googleusercontent.com\/oE2o6xRrlMzc8KeEqpr9rP4jK0F3-9fDHWk8xvEWGoVPODEsNY32Ujh5c3G4QqbY6xJlsEX3NAIvpFe0I7N9gUeXVQUqW-aB3hPBRVZQYoRUrduT6q8RnIaRLwhshcl30g214i8\" alt=\"Diagram: MicroBlaze Image Processing Application.\"\/><figcaption>MicroBlaze Image Processing Application.<\/figcaption><\/figure>\n\n\n\n<p>So, how does an engineer make the choice between the implementation of a hard or soft-core processor?&nbsp;<\/p>\n\n\n\n<p>Performance is always a big factor, but an engineer might also consider application-specific needs, flexibility, security, resource availability, portability, and licensing. <\/p>\n\n\n\n<p>Each of these factors will have a different weight for every individual application, but these are the factors designers and developers should think about when determining the best choice for their particular situation.&nbsp;<\/p>\n\n\n\n<p>To usefully compare processor capabilities, inherent processing power first has to be compared. A benchmark called <strong>Dhrystone MIPS<\/strong> or Millions of Instructions Per Second is used to make this comparison. Lining up the hard and soft cores being considered in a table, it becomes clear that the embedded processors offer higher clock speeds.&nbsp;<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table><tbody><tr><td>Processor<\/td><td>DMIPS\/MHz<\/td><td>Comment&nbsp;<\/td><\/tr><tr><td>Cortex-A53<\/td><td>2.3&nbsp;<\/td><td>Quad or dual processors&nbsp;<\/td><\/tr><tr><td>Cortex-A9<\/td><td>2.3<\/td><td>Dual or single&nbsp;<\/td><\/tr><tr><td>Cortex-R5<\/td><td>1.67<\/td><td>Dual or lockstep<\/td><\/tr><tr><td>MicroBlaze<\/td><td>1.04 \u2013 1.31<\/td><td><\/td><\/tr><tr><td>Cortex-M1<\/td><td>0.8<\/td><td><\/td><\/tr><tr><td>Cortex-M3<\/td><td>1.25<\/td><td><\/td><\/tr><tr><td>RISC-V&nbsp;<\/td><td>1.7&nbsp;<\/td><td>Depends on implementation<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>The needs of the application are equally important; for example, if the processor core only needs to configure IP within the processing system or implement serial communication protocols, then a soft-core-based processor may well be the prefered choice.&nbsp;<\/p>\n\n\n\n<p>On the other hand, for high-performance algorithms that demand powerful processing capabilities, hard-core processors undeniably have a performance advantage.&nbsp;<\/p>\n\n\n\n<p>Another major factor affecting choice may be <strong>security<\/strong>.&nbsp; This is particularly important for<strong> edge applications.<\/strong>&nbsp; Hard processing solutions like the Zynq MPSoC incorporate security measures such as a <strong>Configuration Security Unit<\/strong>, <strong>Secure Boot<\/strong> and <strong>Arm Trust Zone<\/strong>. Soft-core processors often require that separate security protections are added to the programmable logic.&nbsp;<\/p>\n\n\n\n<p>Configuration is one of the biggest points of difference between hard- and soft-core processors: the processor dominates in a hard-core system, booting first and configuring the programmable logic to the desired specifications. <\/p>\n\n\n\n<p>This allows the implementation of several power-saving modes, for example, powering down a processor core, peripherals, or even the entirety of the programmable logic.&nbsp;<\/p>\n\n\n\n<p>By contrast, an FPGA must first be configured to instantiate a soft-core processor. Once that has successfully occurred, the processor can begin operation. The ability of the soft-core processor to implement power down\/power saving schemes is therefore limited, although a lot can still be achieved using lower clock frequencies.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-the-big-little-approach\"><strong>The big.LITTLE Approach<\/strong><\/h2>\n\n\n\n<p>Nonetheless, applications that simultaneously use both hard and soft processors in the same solution are seen with increasing frequency.&nbsp; The image below illustrates this approach.<\/p>\n\n\n\n<p>A <strong>big.LITTLE <\/strong>approach like this focuses the high-performance application processor on the high-level application and delegates real-time applications such as sensor interfacing and motor control to the soft-core processor in the programmable logic.&nbsp;<\/p>\n\n\n\n<p>A big.LITTLE approach like this offers a more responsive solution than an application processor in isolation.&nbsp;<\/p>\n\n\n\n<figure class=\"wp-block-image\"><img decoding=\"async\" src=\"https:\/\/lh3.googleusercontent.com\/2NDBQhseOzrtmimKQq6aVk4WOG7Crej2Nja-U2Ee1cT_fUIlem57Miip55tO7_zAuDqb_Bjce0-RI74CqNZiq24p9PRqKSsdLn_okLacQ7pFr-60GgIFL9E4rRt-yKtKVPa0VSQ\" alt=\"Diagram: Big-Little Approach with the Zynq MPSoC and Arm Corex-M3.\"\/><figcaption>Big-Little Approach with the Zynq MPSoC and Arm Corex-M3.<\/figcaption><\/figure>\n\n\n\n<p>Creating the architecture for a big.LITTLE interface correctly also allows updates to the main application as needed, but avoids changing the code in execution within the little processor. Sensor changes and updates can also be addressed easily by updating the code running in the soft-core processor.&nbsp;<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-software-development\"><strong>Software Development&nbsp;<\/strong><\/h2>\n\n\n\n<p>The <strong>Vivado Design Suite<\/strong> is used in the development of both hard and soft-core processor solutions, to configure the hard-core processor or implement the soft-core solution. Configuration complete, the Xilinx Unified Software Platform, Vitis, can make use of the design description.&nbsp;<\/p>\n\n\n\n<p>Vitis already supports application software for processors in the Zynq-7000 SoC, Zynq MPSoC, and MicroBlaze devices. Development aimed at third-party processors such as Arm Cortex-M1, Cortex-M3, and RISC-V will make use of toolchains provided by the processor core\u2019s creator &#8211;&nbsp; Arm Keil, for example.&nbsp;<\/p>\n\n\n\n<p><strong>JTAG<\/strong> or <strong>Serial Wire<\/strong> interfaces allow users the ability to debug these solutions at the software development stage. Breakpoints, watch registers, and monitor memory locations can all be added, with the result that users can easily identify the root cause of any problem.&nbsp;<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-conclusion\"><strong>Conclusion&nbsp;<\/strong><\/h2>\n\n\n\n<p>Thanks to the range of embedded processors that can be incorporated into programmable logic devices, there is a suitable processor available for each and every use case.&nbsp;<\/p>\n\n\n\n<p>Making a start with these solutions is simple: embedded processor solutions, whether hard- or soft-core, can be created easily &#8211; no need to write even a single line of HDL! Vivado\u2019s IP Integrator allows developers to focus on their application.&nbsp;&nbsp;<\/p>\n\n\n\n<p>Join us for the next instalment in this series as we explore the design tools Xilinx has created to make integrating programmable logic a stress-free process. Or, if you want more technical information about the hardware you can use for your project, visit&nbsp;the <a href=\"https:\/\/eu.mouser.com\/\" target=\"_blank\" rel=\"noreferrer noopener\">Mouser website<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>In the first article in this series co-produced with Mouser Electronics, we explored the range of FPGA devices produced by Xilinx and discussed the benefits of adopting such a system for developers, engineers, and end-users alike. Now, let\u2019s dig a little deeper and discover what makes an FPGA tick. The programmable logic found in FPGAs&#8230; <a class=\"more-link\" href=\"https:\/\/www.codemotion.com\/magazine\/ai-ml\/machine-learning\/embedded-processing-in-programmable-logic\/\">Read more<\/a><\/p>\n","protected":false},"author":121,"featured_media":15100,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_editorskit_title_hidden":false,"_editorskit_reading_time":8,"_editorskit_is_block_options_detached":false,"_editorskit_block_options_position":"{}","_uag_custom_page_level_css":"","_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"categories":[35],"tags":[],"collections":[],"class_list":{"0":"post-15096","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-machine-learning","8":"entry"},"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.9 (Yoast SEO v26.9) - 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