{"id":15254,"date":"2021-06-30T12:46:53","date_gmt":"2021-06-30T10:46:53","guid":{"rendered":"https:\/\/www.codemotion.com\/magazine\/?p=15254"},"modified":"2023-06-07T18:07:09","modified_gmt":"2023-06-07T16:07:09","slug":"understanding-xilinx-design-tools","status":"publish","type":"post","link":"https:\/\/www.codemotion.com\/magazine\/ai-ml\/understanding-xilinx-design-tools\/","title":{"rendered":"Understanding Xilinx Design Tools"},"content":{"rendered":"\n

In the second article<\/a> in this series co-produced with Mouser Electronics<\/a>, we saw how to implement embedded processors with programmable logic devices. Now, let\u2019s see how vendors have lowered programmable logic tools<\/strong>‘ learning curve.<\/p>\n\n\n\t\t\t\t

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  1. Design implementation and verification<\/a>
  2. Vivado Design Suite<\/a>
  3. Application Software Creation<\/a>
  4. Acceleration\u00a0<\/a>
  5. AI and beyond<\/a>
  6. Conclusion\u00a0<\/a><\/ol>\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\n\n\n

    Design implementation and verification<\/h2>\n\n\n\n

    Indeed, it\u2019s often daunting to face a new development challenge, especially if the toolchain or process are unfamiliar, and implementing a design in a programmable logic device <\/strong>can appear especially so at times. <\/p>\n\n\n\n

    FPGA implementation tools <\/strong>have frequently been seen as demanding a steep learning curve and deep logic design skills if you want to end up with a solution that works. <\/p>\n\n\n\n

    However, programmable logic vendors have expended significant energy on this subject over the last decade. The result? More user-friendly toolchains<\/strong> that offer a shallower learning curve, and enable the use of higher-level languages, opening this area to a wider user base, and the field continues to evolve<\/p>\n\n\n\n

    A range of tools are available for design implementation and verification that are aimed specifically at developing programmable logic solutions targeting Xilinx devices. <\/p>\n\n\n\n

    These tools not only support design verification and programming file creation but also allow embedded Linux <\/em>operating systems and artificial intelligence<\/em> and machine learning solutions<\/em> to be implemented. <\/p>\n\n\n\n

    This technology stack opens the door to the development of solutions for both traditional FPGA and heterogeneous systems on chips that combine programmable logic with high-performance Arm processor cores. <\/p>\n\n\n\n

    Depending on a user\u2019s preferred entry point, this unusual stack also enables implementation using traditional hardware design language <\/strong>(HDL) capture and a higher-level system-optimising compiler approach. <\/p>\n\n\n\n

    The design tools\u2019 interplay can be seen in the image below. Each element of the technology stack offers a specific capability. <\/p>\n\n\n\n

    \"Image<\/figure>\n\n\n\n

    Vivado Design Suite<\/h2>\n\n\n\n

    At the base of the technology stack is Vivado<\/strong>. Vivado allows designs to be captured using VHDL or Verilog, and the HDL design to be synthesised to the target device before placing and routing and generating the programming file. <\/p>\n\n\n\n

    The IP integrator<\/strong> at Vivado\u2019s heart permits designers to capture designs quickly and easily using IP, whether provided by Xilinx or third parties, or custom-developed. This IP can be defined using HDL or a higher-level approach that uses Vitis HLS can be taken, enabling the development of IP blocks using C and C++. <\/p>\n\n\n\n

    Vivado\u2019s focus is implementation, but a complete development ecosystem is on offer.  Vivado provides several capabilities that contribute greatly to the overall development of programmable logic. <\/a><\/p>\n\n\n\n

    For any design, a key feature is the ability to guarantee the functional performance of the HDL prior to implementation. To verify HDL <\/strong>functionality, Vivado provides an HDL simulator. Depending upon the stage of implementation, the test bench can be applied against the RTL, the synthesised netlist, or against the implemented netlist with associated timing information.  <\/p>\n\n\n\n

    Vivado is also the tool used to debug designs on the hardware, due to the support for integrated logic analysers (ILA<\/strong>), Virtual IO (VIO<\/strong>), and JTAG to AXI IP<\/strong> it offers. Designers are enabled to instrument the programmable logic design and observe behaviour at run time in the actual system. <\/p>\n\n\n\n

    Vivado\u2019s implementation and simulation capabilities are also used by tools further up  the development stack.<\/p>\n\n\n\n

    Application Software Creation<\/h2>\n\n\n\n

    When a heterogeneous SoC <\/strong>or FPGA <\/strong>which contains a soft processor core such as a MicroBlaze enters the picture, the higher levels of the stack need to come into play to create the operating systems\u2019 application software. The relationship between Vivado, PetaLinux and Vitis is illustrated below.<\/p>\n\n\n\n

    \"Graph<\/figure>\n\n\n\n

    Hard and soft-core processor implementations both require operating systems to be generated and application software to be developed. Such software can be developed to run on a BareMetal, real-time operating system (FreeRTOS<\/strong>) or on an embedded Linux solution.  <\/p>\n\n\n\n

    Development and debugging of the software can be achieved by using Xilinx\u2019s Vitis unified software platform. Vitis provides two development flows – embedded and accelerated. <\/p>\n\n\n\n

    The embedded flow allows developers to create software solutions for any supported embedded processor. The accelerated flow enables users of Xilinx SoC and Acceleration cards <\/strong>to accelerate functionality from the processor system to the programmable logic.<\/p>\n\n\n\n

    Vitis developers can import Vivado designs to create embedded solutions when using the embedded flow. To simplify the debugging of the embedded systems, Vitis offers a complete debugger capable of supporting multi-core operation. <\/p>\n\n\n\n

    The software application includes operations with elements of the programmable logic design, meaning that it is also possible to cross probe and breakpoint with ILAs within the programmable logic in order to gain a greater understanding of the hardware\/software interaction.<\/p>\n\n\n\n

    Developers who prefer an embedded Linux solution utilize the PetaLinux build tool. PetaLinux a build system rather than a Linux distribution.  <\/p>\n\n\n\n

    Consequently, developers can configure an embedded Linux system that includes the drivers and device tree entries to work with the programmable logic design using this tool. <\/p>\n\n\n\n

    With a PetaLinux operating system <\/em>in place for a Xilinx SoC, the developer can deploy the PYNQ framework<\/strong>. This enables Python <\/em>and Jupiter Notebooks<\/em> to be used with programmable logic. PYNQ is perfect for rapid prototyping due to the many drivers available in the Python environment to work with IP in the programmable logic, which significantly reduces the software development required. <\/p>\n\n\n\n

    The higher levels of the technology stack such as the Vitis acceleration capabilities and Vitis AI require a hardcore processor and embedded Linux solution or an Alveo acceleration card to access. <\/p>\n\n\n\n

    Acceleration <\/h2>\n\n\n\n

    Vitis<\/strong>\u2019 ability to accelerate applications into the programmable logic using OpenCL <\/em>also provides an entry point for solutions that use both the processing system and the programmable logic. <\/p>\n\n\n\n

    To make best use of this capacity, an acceleration platform must be available to Vitis. Acceleration platforms can be created in Vivado for custom hardware and are widely available for download  on many development boards. <\/p>\n\n\n\n

    The acceleration platform<\/strong> makes several system resources such as AXI interfaces, processor interrupts, and clocks available to the Vitis compiler. These resources are connected to the accelerated elements of the design in order to facilitate access from the processing system.  <\/p>\n\n\n\n

    Vitis used the OpenCL framework to achieve this acceleration. An open industry standard developed by The Khronos Group<\/em>, OpenCL enables parallel computing of heterogeneous systems. The OpenCL model includes a host – usually an x86 system, and an OpenCL device that is often called a kernel. <\/p>\n\n\n\n

    OpenCL provides parallel processing and application acceleration while the host manages overall application execution. An FPGA, DSP, GPU or CPU<\/strong> can be used to provide this parallel processing. Using OpenCL enables the source code that is running on the OpenCL device to be retargeted without any changes to the source code itself.  <\/p>\n\n\n\n

    OpenCL provides OpenCL APIs<\/strong> to support this model. These can be compiled into the host application by means of standard C compilers such as GCC or G++. <\/p>\n\n\n\n

    OpenCL devices are developed using the OpenCL C language, derived from ISO C99<\/em>.  The language is not C, however, because the standard libraries are difficult to support across all the potential OpenCL devices. Consequently, each OpenCL device has a specific, vendor-provided OpenCL compiler. For Xilinx devices, this is provided by Vitis. <\/p>\n\n\n\n

    The following architectures are comprised of such heterogeneous systems in the Xilinx ecosystem: <\/p>\n\n\n\n